The present invention relates to a semiconductor integrated circuit device and to a technique for the manufacture thereof, and, more particularly, the invention relates to a technique which is effective for application to a dynamic random access memory (DRAM) requiring a storage holding operation, and which is suitable for high integration.
DRAMs are commonly classified as a trench type or a stacked type relative to their basic structures. The trench type is one wherein information storage capacitative elements (capacitors) are formed inside trenches defined in a substrate, whereas the stacked type is one wherein information storage capacitative elements are formed above transfer transistors (memory cell selection MISFETs (Metal Insulator Semiconductor Field Effect Transistors)) on the surface of a substrate. The stacked type is further classified into a CUB (Capacitor Under Bit-line) type wherein information storage capacitative elements are placed below bit lines and a COB Capacitor Over Bit-line) type wherein they are placed thereabove. Products of 64 Mbits or more, which currently are being mass produced, are respectively of the stacked type and are characterized by excellent reduction of the cell area. The COB type is becoming a mainstream device.
A structure of a DRAM having COB type memory cells is as follows.
Namely, the memory cells of the DRAM having the COB type memory cells are respectively placed at points where a plurality of word lines intersect with a plurality of bit lines disposed over a main or principal surface of a semiconductor substrate in matrix form. Each memory cell comprises one memory cell selection MISFET and one information storage capacitative element electrically directly connected to it. The memory cell selection MISFET is formed in an active area or region whose periphery is surrounded by device or element separation regions, and principally comprises a gate oxide film, a gate electrode formed integrally with each word line, and a pair of semiconductor regions constituting a source and a drain. The bit line is placed above the memory cell selection MISFET and is electrically connected to one of a source and drain shared between adjacent memory cell selection MISFETs aligned in the direction in which the memory cell selection MISFET extends. The information storage capacitative element is similarly placed above the memory cell selection MISFET and is electrically connected to the other of the source and drain. In order to replenish a reduction in the stored amount of electrical charge (Cs) of each information storage capacitative element, incident to a micro-fabrication of each memory cell, a lower electrode (storage electrode) of the information storage capacitative element placed above the bit line is processed into cylindrical form to thereby increase its surface area, and a capacitive insulating film and an upper electrode (plate electrode) are formed thereabove.
If the area of each memory cell of the conventional DRAM is designed so as to take up a minimum space, it is then necessary to form connecting hole (hereinafter called capacitive-electrode connecting hole) patterns for connecting the lower electrodes of the information storage capacitative elements to the active regions or the connecting plugs on the active regions and bit line patterns in minimum processing sizes. However, a large problem occurs in terms of their processing in order to form these patterns in the minimum processing sizes. This will be explained below with reference to the drawings. FIG. 72 is a cross-sectional view for describing the problem on the processing of each capacitive-electrode connecting hole and shows a cross section of a memory cell portion as seen in the direction orthogonal to the direction in which each bit line extends.
Namely, when each memory cell of a DRAM includes an active region 203 surrounded by separation areas or regions 202 of a main or principal surface of a semiconductor substrate 201, a semiconductor region 204 which is formed over the active region 203 and serves as the source and drain of a memory cell selection MISFET, a connecting plug 205 formed over the semiconductor region 204, an information storage capacitative element C formed over the active region 203 and composed of an upper electrode 206, a capacitive insulating film 207 and a lower electrode 208, and a bit line 209 formed between the connecting plug 205 and the information storage capacitative element C as shown in FIG. 72(a). It is necessary to form the active region 203, the bit line 209, and the capacitive-electrode connecting hole 210 for connecting the connecting plug 205 and the lower electrode 208 in minimum processing sizes for the purpose of forming each memory cell of the DRAM in a minimum processing size. However, a margin 211 for alignment with the bit line 209 at the processing of the capacitive-electrode connecting hole 210 cannot be ensured sufficiently. Therefore, there is a possibility that the lower electrode 208 and the bit line 209 will be short-circuited due to a displacement in alignment or a variation in processing size. As a result, the probability that a reduction in manufacturing yield will occur, increases.
To avoid such a problem, there is provided a method of effecting the processing of the capacitive-electrode connecting hole 210 on the bit line 209 on a self-alignment basis. This is a method of covering an upper portion of each bit line 209 with a silicon nitride film 212, protecting the sides of the bit line 209 with sidewall spacers 213 composed of the silicon nitride film, controlling or adjusting etching conditions upon etching of silicon oxide films 214 and 215 by patterns for the capacitive-electrode connecting holes 210 to set a selection ratio of the silicon nitride film to each silicon oxide film sufficiently high, thereby etching only the silicon oxide films without cutting away the silicon nitride film so as to prevent the exposure of each bit line 209, as shown in FIG. 72(b). According to the method, even if an alignment displacement occurs in the pattern for each capacitive-electrode connecting hole 210, the lower electrode 208 and the bit line 209 can be prevented from being short-circuited.
In the present structure, however, the thickness of the silicon nitride film 212 is required in addition to the thickness of the bit line 209 and the thickness from the connecting plug 205 to the surface of the silicon oxide film 214 increases, as shown in FIG. 72(b). Therefore, a new problem arises in that the height 216 up to the information storage capacitative element C increases and hence the height of each cell itself becomes high, thereby increasing a step-like offset between the cell and a peripheral circuit region.
An object of the present invention is to provide a technique which is capable of reducing the width of a bit line beyond a processing limit of photolithography.
Another object of the present invention is to provide a structure of a semiconductor integrated circuit device which is capable of preventing short circuits in a bit line and a lower electrode of an information storage capacitive element without increasing the height of a memory cell, and a method of manufacturing the same.
A further object of the present invention is to provide a technique which is capable of reducing the capacitance of a bit line and to provide a semiconductor integrated circuit device which is high in detection sensitivity and excellent in noise resistance.
A still further object of the present invention is to provide a structure of a semiconductor integrated circuit device, which adopts simple flat or plane patterns suitable for photolithography and a technique capable of improving the processing margin.
A still further object of the present invention is to provide a structure of a semiconductor integrated circuit device which is suitable for high integration of a DRAM and a method of manufacturing the same, and a technique capable of improving the reliability, yields and performance of the semiconductor integrated circuit device.
The above and other objects and novel features of the present invention will become apparent from the following description and the accompanying drawings.
Summaries of typical aspects and features of the present invention as disclosed in the present application will be described briefly as follows:
(1) A semiconductor integrated circuit device according to the present invention is provided which comprises a semiconductor substrate, gate electrodes which are respectively formed on active regions each surrounded by separation regions of a principal surface of the semiconductor substrate through a gate insulating film and serve afford lines of a DRAM, for example, channel regions placed below the gate electrodes respectively, memory cell selection MISFETs including first and second semiconductor regions formed with the each channel region interposed therebetween, metal interconnections which are electrically connected to the first semiconductor region and serve as bit lines, for example, and information storage capacitative elements electrically connected to the second semiconductor region and formed in a layer above the metal interconnections, and wherein wiring grooves are defined in a first insulating film formed over the gate electrodes, and each metal interconnection is formed so as to be embedded in each wiring groove and is located above the gate electrodes in a region defined between the gate electrodes.
According to such a semiconductor integrated circuit device, since the metal interconnection is formed so as to be embedded in the wiring grooves defined in the first insulating film, the width of the metal interconnection can be made thin as compared with the case in which the metal interconnection is formed by patterning. Namely, the formation of the wiring grooves in the first insulating film by patterning facilitates a micro-fabrication, which makes it possible to form the width of the metal interconnection thin as compared with the case in which a metal film is deposited over the first insulating film and subjected to patterning to thereby form each metal interconnection.
As a result, owing to the processing of the capacitive electrode connecting holes defined between the metal interconnections, the metal interconnections are not exposed, and a lower electrode of the information storage capacitative element and each metal interconnection corresponding to the bit line are prevented from being short-circuited, whereby the reliability of the semiconductor integrated circuit device can be improved. Incidentally, there is no need to adopt a self-aligned processing method upon processing of the capacitive electrode connecting holes, and the above-described inconvenience of increasing the height of each memory cell is not developed either.
Further, the width of each metal interconnection can be reduced so that the interval between the metal interconnections can be made long. The capacitance between the metal interconnections, i.e., the capacitance of each bit-line, is reduced to improve the sensitivity of detection of a stored electrical charge. Moreover, the speed of response of a transistor electrically connected to the bit line is improved so that the performance of the semiconductor integrated circuit device can be enhanced. In addition, the metal interconnections are located above the gate electrodes so that the capacitance between the metal interconnection and each gate electrode can be reduced.
(2) The semiconductor integrated circuit device further includes first connecting holes defined in a second-insulating film lying between the metal interconnections and the gate electrodes, and conductive connecting plugs respectively formed within the first connecting holes and electrically connected to the first semiconductor region, which can be constructed so that the bottom of each metal interconnection is electrically connected to an upper portion of each connecting plug at the bottom of the wiring groove. Alternatively, the semiconductor integrated circuit device further includes a third insulating film located below the first insulating film and formed so as to be buried between the gate electrodes, second connecting holes defined in the third insulating film on the first semiconductor region, and a conductive film for covering the second connecting holes, which can be constructed so that the bottom of the metal interconnection is electrically connected to an upper portion of the conductive film at the bottom of each wiring groove.
According to such a semiconductor integrated circuit device, the metal interconnection corresponding to the bit line, and the first semiconductor region can be connected to each other through the connecting plugs or conductive film. Further, patterns for the active regions or metal interconnections can be set to plane or flat patterns having linear configurations, which extend in a first direction. While the need for the formation of the active regions and the metal interconnections in the minimum processing sizes to minimize the area of each memory cell is as described above, the interference of light at the time of exposure during photolithography can be limited to a minimum to increase the processing margin by bringing these patterns to simple linearly-configured flat patterns. It is thus possible to improve the manufacturing yields of the semiconductor integrated circuit device and enhance the reliability of the semiconductor integrated circuit device.
When the metal interconnections and the first semiconductor region are connected to each other through the connecting plugs or conductive film, the patterns for the active regions and metal interconnections are configured as flat patterns having the linear configurations extending in the first direction and configured in such a flat layout as to be inserted between the mutually adjacent patterns as seen in a second direction orthogonal to the first direction. Further, each connecting plug or the conductive film can be placed in a pattern extending from-the first semiconductor region lying in the center of each active region to the metal interconnection portion in the second direction. In such a case, the patterns for the active region and the metal interconnection can be both placed as simple linear patterns to improve the processing margin, and the first semiconductor region and the metal interconnection can be reliably connected to each other by using the connecting plugs or conductive film.
Since, in these cases, the wiring grooves are defined and the metal film is embedded therein to form the metal interconnections, the connecting plugs and the upper portion of the conductive film can be exposed simultaneously upon processing of the wiring grooves. There is also no need to form the connecting holes for connecting to the connecting plugs or the conductive film. As a result, there is no need to form the insulating film for covering the connecting plugs or the conductive film, and the height can be lowered by the thickness of the insulating film. A step for processing the connecting holes for connecting to the connecting plugs or the conductive film is omitted and hence the process can be simplified.
(3) In the semiconductor integrated circuit device, the active regions and the metal interconnection are formed in substantially linear flat patterns extending in the first direction, and one or both of the active regions and the metal interconnection have regions extending in the second direction orthogonal to the first direction. The metal interconnection and the first semiconductor region are directly connected to each other through each of third connecting holes defined in portions below the wiring grooves in the regions.
(4) In the semiconductor integrated circuit devices described in the paragraphs (1) through (3), sidewall spacers corresponding to insulators can be respectively formed over side walls of the wiring grooves or the third connecting holes, and the width of each metal interconnection can be set narrower than the width of each wiring groove by a width corresponding to the thickness of each sidewall spacer.
According to such a semiconductor integrated circuit device, the width of the metal interconnection can be formed thinner as compared with the case in which the metal interconnection is formed so as to be simply embedded in each wiring groove. Thus, the above-described effect (1) can be brought about more reliably and noticeably.
Incidentally, the height of the surface of the metal interconnection in this case can be set lower than that of the surface of the first insulating film. This corresponds to a metal interconnection which is excessively polished where the metal interconnection is formed by a CMP process or method in a process step for forming the metal interconnection, as will be described later. Namely, the sidewall spacers are normally thin in thickness in the vicinity of the upper portion of each wiring groove and thick in thickness at the bottom of the wiring groove. There is a possibility that under such a condition, the effect of reducing the width of the metal interconnection by the sidewall spacers will not be obtained pronouncedly if the metal interconnection is formed up to the upper portion of each wiring groove, i.e, a region in which the thickness of each sidewall spacer is thin. Therefore, excessive polishing is performed upon formation of the metal interconnection to thereby polish the metal interconnection up to a region in which the thickness of the sidewall spacer becomes sufficiently thick.
The sidewall spacers can be composed of silicon oxide film or a silicon nitride film. Since the width of the metal interconnection is made thin by the sidewall spacers employed in the present invention, the need for utilization of the self-aligned processing method upon processing of the capacitive-electrode connecting holes is eliminated as described above. Therefore, the silicon oxide film is used as a material for defining the capacitive-electrode connecting hole, whereas there is no need to use the silicon nitride film for the sidewall spacers. However, when the silicon nitride film is used, the exposure of the metal interconnection can be avoided by the processing of each capacitive-electrode connecting hole even if a large displacement in alignment temporarily occurs and a variation in process conditions occurs. On the other hand, if the silicon oxide film is used for the sidewall spacers, then the capacitance between the metal interconnections serving as the bit lines can be reduced due to a low dielectric constant of the silicon oxide film.
In the semiconductor integrated circuit devices described in the paragraphs (1) through (3), a fourth insulating film having an etching selection ratio with respect to the first insulating film or the sidewall spacers may be formed at the bottom of each wiring groove. In such a case, the fourth insulating film can be utilized as an etching stopper upon definition of the wiring grooves in the first insulating film. Further, the fourth insulating film can be used as an etching stopper upon formation of the sidewall spacers. Incidentally, the first insulating film or the sidewall spacers can be composed of a silicon oxide film, and the fourth insulating film can be composed of a silicon nitride film.
(5) A method of manufacturing a semiconductor integrated circuit device, according to the present invention, comprising a semiconductor substrate, gate electrodes respectively formed on active regions each surrounded by separation regions of a principal surface of the semiconductor substrate through a gate insulating film, channel regions placed below the gate electrodes respectively, first and second semiconductor regions formed with each channel region interposed therebetween, metal interconnections each electrically connected to the first semiconductor region, and information storage capacitative elements electrically connected to the second semiconductor region and formed in a layer above the metal interconnections, comprises the following steps: (a) a step of forming the separation regions over the main surface of the semiconductor substrate, successively forming an insulating film and a conductive film and patterning the conductive film to thereby form the gate electrodes; (b) a step of ion-introducing an impurity into both ends of the gate electrodes to thereby form the first and second semiconductor regions; (c) a step of forming a first insulating film over the entire surface of the semiconductor substrate and defining wiring grooves in the first insulating film; (d) a step of depositing a metal film over the first insulating film including the interior of each wiring groove and removing each metal film lying in a region other than the wiring grooves to thereby form each metal interconnection; and (e) a step of depositing a fifth insulating film for covering the entire surface of the semiconductor substrate and forming each information storage capacitative element over the fifth insulating film, whereby the metal interconnection is positioned above each gate electrode in a region between the gate electrodes.
According to such a manufacturing method, the semiconductor integrated circuit device described in the paragraph (1) can be manufactured. According to such a manufacturing method as well, it is unnecessary to provide the silicon oxide film 215 and the silicon nitride film 212 shown in FIG. 72(b), that led up to the increase in the height of each memory cell in the prior art. As a result, the height of the memory cell can be reduced and the step-like offset between the memory cell and the peripheral circuit region can be less reduced so as to increase a photolithography margin at the patterning of the metal interconnection formed above the information storage capacitative element. Further, failures such as a break in the metal interconnection, etc. can be reduced. The positioning of the metal interconnection above the gate electrodes allows a reduction in the capacitance between the metal interconnection and each gate electrode.
The above-described manufacturing method includes, prior to the step (c), a step of forming a second insulating film over the entire surface of the semiconductor substrate so as to fill in between the gate electrodes and defining first connecting holes in the second insulating film on the first and second semiconductor regions, and a step of forming connecting plugs connected to the first and second semiconductor regions so as to be embedded in the first connecting holes respectively. Owing to the formation of the wiring grooves in the step (c), upper portions or upper surfaces of the connecting plugs connected to the first semiconductor region can be exposed at the bottoms of the wiring grooves.
According to such a manufacturing method, a semiconductor integrated circuit device having the connecting plugs for connecting the first semiconductor region and the metal interconnection can be fabricated. Further, portions for connecting to the connecting plugs can be formed simultaneously with the formation of the wiring grooves. Therefore, other process steps used for the formation of the connecting holes for exposing the connecting plugs, etc. can be omitted. Thus, the process of manufacturing the semiconductor integrated circuit device can be simplified.
The above-described manufacturing method further includes, prior to the step (c), a step of depositing a third insulating film for covering the gate electrodes and defining second connecting holes in the third insulating film on the first semiconductor region, and a step of depositing a conductive film over the third insulating film including the interior of each second connecting hole and patterning the conductive film so as to cover the second connecting holes. Owing to the definition of the wiring grooves in the step (c), some of the conductive film can be exposed at the bottoms of the wiring grooves.
According to such a manufacturing method, a semiconductor integrated circuit device having a conductive film for connecting the first semiconductor region and the metal interconnection can be manufactured. Even by the present method, portions for connecting to the conductive film can be formed simultaneously with the definition of the wiring grooves, so that the manufacturing process can be simplified. According to the present method, a flattening process using a CMP method can be performed with a reduced number of steps as compared with the process for forming the connecting plugs. Namely, a method of forming the connecting plugs needs to flatten the insulating film before the connecting holes are defined in which the connecting plugs are to be formed, whereas a method of forming the conductive film according to the present method requires no flattening of the insulating film with the conductive film formed thereon. It is therefore possible to omit a CMP process step in the process of forming the insulating film, antecedent to the patterning of the conductive film. It is necessary to make the insulating film thick in order to ensure a flatness over the entire surface of the substrate in the CMP process step. Since, however, the CMP process step is omitted in the present method, the thickness of the insulating film can be reduced correspondingly, thereby making it possible to limit the height of each memory cell to as low a value as possible.
The above described manufacturing method further includes, after the step (c), a step of defining third connecting holes having flat patterns which overlap with wiring groove regions and expose the first semiconductor region. The metal film can be formed even inside the third insulating film upon deposition of the metal film in the step (d).
According to such a manufacturing method, a semiconductor integrated circuit device constructed so that the metal interconnection and the first semiconductor region are directly connected to each other, can be manufactured. Namely, the metal interconnection can be formed by a so-called dual damascene method.
In the above-described manufacturing method of forming the connecting plugs or the conductive film and exposing the connecting plugs or part of the conductive film simultaneously with the definition of the wiring grooves, the metal interconnection corresponding to each bit line and the connecting plugs or the conductive film are directly connected to each other at the bottom of each wiring groove. Therefore, the insulating film for separating the connecting plugs or conductive film from the metal interconnection becomes unnecessary and the connecting holes defined in the insulating film are also inevitably unnecessary. As a result, the height of a cell can be reduced as a result of the elimination of the need for the insulating film, and the number of masks can be reduced as a result of the lack of any need for the connecting holes.
(6) A method of manufacturing a semiconductor integrated circuit device, according to the present invention includes, prior to the step (d) in the manufacturing method described in the paragraph (5), a step of depositing a sixth insulating film having a thickness which is less than one half the width of each wiring groove over a first insulating film including the interior of wiring grooves or third connecting holes, and subjecting the sixth insulating film to anisotropic etching, thereby forming sidewall spacers on side walls of the wiring grooves or the third connecting holes respectively.
According to such a manufacturing method, the sidewall spacers can be respectively formed on the side walls of the wiring grooves so as to reduce the width of the metal interconnection. Namely, since the wiring grooves are defined by etching processing of the first insulating film using photolithography, they cannot be formed below a processing limit of photolithography. However, if the sidewall spacers are formed on the side walls of the wiring grooves as in the present method, then the interval interposed between the sidewall spacers is below the processing limit of photolithography. Thus, the width of each metal interconnection embedded into the interval is formed below the processing limit. It is therefore possible to ensure a sufficient processing margin upon formation of each capacitive-electrode connecting hole and thereby enhance production yields of the semiconductor integrated circuit device and improve the reliability thereof.
Incidentally, the metal film for forming the metal interconnection is removed by polishing using a CMP process. The polishing is excessively performed to allow the occurrence of dishing in the surface of the metal interconnection lying in each wiring groove. Alternatively, the metal film for forming the metal interconnection is removed by polishing using the CMP process and the polishing is excessively done so that even width-narrow portions of the sidewall spacers above the wiring grooves can be removed together with the metal film. In such a case, the width of the metal interconnection can be effectively made thin without forming the metal interconnection over thickness-reduced portions of the sidewall spacers, which are located above the wiring grooves.
In the above-described manufacturing method, a fourth insulating film having an etching selection ratio with respect to the first insulating film or the sixth insulating film is formed in any layer between the gate electrodes and the first insulating film. The fourth insulating film can be used as an etching stopper upon definition of the wiring grooves in the first insulating film or upon formation of the sidewall spacers by the anisotropic etching of the sixth insulating film. A silicon oxide film can be suggested by way of example for the first and sixth insulating films, and a silicon nitride film can be suggested by way of example for the fourth insulating film.
In the above-described manufacturing method, a step for processing connecting holes for connecting the information storage capacitative elements to the second semiconductor region placed therebelow or the connecting plugs on the second semiconductor region can include a first step of depositing a first coating having an etching selection ratio with respect to the first and fifth insulating films over the fifth insulating film, a second step of defining openings in the first coating on the second semiconductor region, a third step of depositing a second coating having a thickness of less than one half the diameter of each opening and having an etching selection ratio with respect to the first and fifth insulating films, a fourth step of subjecting the second coating to anisotropic etching to thereby form sidewall spacers composed of the second coating on inner walls of the openings, and a fifth step of etching the fifth insulating film and the insulating film lying therebelow with the sidewall spacers of the first and second coatings as hard masks.
According to such a manufacturing method, the information storage capacitative elements can be processed in processing sizes below the processing limit of photolithography. Further, short circuits in the lower electrode of the information storage capacitative element and the metal interconnection (bit line) can be reliably prevented in synergy with the above-described method capable of reducing the width of the metal interconnection.